搜索资源列表
cpld
- CPLD与电子CAD报告 VHDL中的并行语句、进程 信号、变量、顺序语句 分频器、计数器、译码器、状态机 数字钟综合设计-CPLD and VHDL electronic CAD report in parallel statement, the process signals, variables, sequential statements divider, counter, decoder, an integrated digital clock state machine des
szz
- 基于CPLD的数字钟,用VHDL语言编写,数码管显示,可调时调分,具有整点报时功能。-CPLD-based digital clock, using VHDL language, the digital display, an adjustable transfer points, the whole point timekeeping function.
VHDL_doc
- VHDL入门的程序,包括数码管显示,交通灯的实现,多功能数字钟,数字频率计等-VHDL entry procedures, including digital display, realize traffic lights, multifunction digital clock, digital frequency meter, etc.
FPGA
- 数字钟的VHDL语言程序,包含了好几个模块,是毕业设计的优秀程序,值得下载!-VHDL language program of digital clock, contains several modules, is an excellent program, graduation design is worth to download!
clock
- VHDL语言,数字钟实现时分秒计数,能够通过按键调整时间-VHDL language, when every minute counts achieve digital clock, the time can be adjusted through the key
shuzizhong3
- 数字钟VHDL软件设计,包含多种功能,报时,12,24切换,调时-The design of VHDL digital clock software, including a variety of functions, timer, 12,24 switch, adjustable
clock
- 用VHDL 语言设计数字钟,实现在数码管上显示分钟和秒,并且可以手动调节分钟, 实现分钟的增或者减。该设计包括以下几个部分: (1)分频电路的设计,产生1Hz 的时钟信号,作为秒计时脉冲; (2)手动调节电路,包括“时增”“时减”“分增”“分减”。 (3)时分秒计时电路。 (4)7 段数码管显示电路。 将 SW1 和SW2 初始状态均置为高电平。拨动开关SW1 到低,分钟进行加计数,秒停 止计数,当计数到59 时,从00 开始重新加计数,将SW1 拨动到高时,在当前状
digital-clock
- vhdl文件,实现数字钟,以及其顶层设计图-This package contains the VHDL file, can realize the digital clock, contains the top-level design
FPGA_exp2
- 调节数码管显示的文件,适用于CYCLONE II 开发板, 用VHDL语言编写,非常适合移植进数字钟中以实现调节时间的功能。 多模块设计简单明了。-Adjust digital display files for CYCLONE II development board, using VHDL language, it is very suitable for transplantation into digital clock to realize the function of regula
EDA实验程序
- VHDL语言编写简单EDA实验程序,如数字钟,,译码器,,动态扫描数码管(VHDL language, simple EDA experimental procedures)